Hardware Details

These are the hardware specifics of the project so far. Other things will be stuck in where it's not too hard to fit them.

Memory Map

Both memory chips in the system are actually 1Mb units, as these are easy to get hold of and decoding is simple. Also, only a little rewiring is needed to use more or less Flash or RAM. They're also not that expensive when compared to smaller capacity chips, especially if you'd need several chips to get where you're going memory-wise.

From To Memory Device
0x0000 0x3FFF Flash ROM
0x4000 0xFFFF Static RAM

I/O Map

I/O addresses are decoded with a 3-to-8 decoder on the top 3 bits of the bottom half of the address bus (hence the 0x20 steps). This imposes a limit of 8 devices, but extra decoding of the lower address lines can be used to exceed this.

From To I/O Device
0x00 ? Reserved for interval timer
0x20 0x27 16C550 UART
0x40 0x42 ATA/IDE Interface


Although not implemented yet, the idea is to send 8 IRQ lines through a latch, an 8-input (N)OR gate, and a 8-3 priority encoder. The resulting 3 lines are then to be connected to the data bus (lines 1 thru 3) via a tri-state buffer for use with the Z80's interrupt mode 2.

IRQ Device
0 Reserved for interval timer
1 16C550 UART