Hardware Details

Both memory chips in the system are actually 1Mb units, as these are easy to get hold of and decoding is simple. Also, only a little rewiring is needed to use more or less Flash or RAM. They're also not that expensive when compared to smaller capacity chips, especially if you'd need several chips to get where you're going memory-wise.

I/O addresses are decoded with a 3-to-8 decoder on the top 3 bits of the bottom half of the address bus (hence the 0x20 steps). This imposes a limit of 8 devices, but extra decoding of the lower address lines can be used to exceed this.

Although not implemented yet, the idea is to send 8 IRQ lines through a latch, an 8-input (N)OR gate, and a 8-3 priority encoder. The resulting 3 lines are then to be connected to the data bus (lines 1 thru 3) via a tri-state buffer for use with the Z80's interrupt mode 2.